FIGS. 1A and 1B are cross-sectional views of a semiconductor device according to the prior art.
FIG. 1A is a cross-sectional view of a semiconductor device comprising a high-power chip 11 and a heat sink 17. Bumps are formed on the face of the chip with the elements, and are bonded to TAB (Tape Automated Bonding) leads 12. This assembly is mounted onto and connected with a layer-built ceramic package 13. A large number of regularly spaced surface mount pins 14 project perpendicularly from an underside of the ceramic package. Power is supplied, and signals are input and output through the pins 14.
The chip 11 is encased in a metal cap 15 with its top side partially exposed. A heat sink 17 is soldered or brazed onto a top side of the chip 11, through a metal plate 16. The metal plate 16 is made of a material such as CuMo, in an attempt to make compatible the coefficients of thermal expansion of the chip 11 and of the aluminum heat sink 17.
FIG. 1B is a partial cross-sectional view of the package shown in FIG. 1A. The ceramic package 13 is constructed of ceramic layers on which is formed a pattern 13a or a power plane 13b. The pattern 13a and the power plane 13b are connected to corresponding pins 14 in the same process that the chip 11 is connected to the TAB leads 12 on which the chip is mounted by means of the bumps.
The semiconductor device illustrated in FIGS. 1A and 1B is of a PGA (Pin Grid Array) type designed for increased pin population and high pin density, allowing a plurality of leads 14 to project from the underside of the package 13.
When surface mounting the semiconductor device onto a board, it is necessary to visually confirm whether device has been successfully connected to the board. Since visual inspection is performed by microscopes and other means, the pins 14 are provided at a periphery of the underside of the ceramic package 13, within the range where visual inspection is possible, as shown in FIGS. 1A and 1B.
There is a disadvantage in this, in that visual inspection is limited to 4-6 rows of pins, prohibiting pin array placement toward the center region, and creating an area that is not usable.